LSN2-T/30-D12-C【PDF 11/16 页】CONV DC/DC 150W 30A 0.8-5V SIP

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LSN2-T/30-D12 Series

DOSA-SIP, 30A POL DC/DC Converters

In Figure 10, two POLs ramp up at the same rate until they reach their

different respective ?nal set point voltages. During the ramp, their voltages

are nearly identical. This avoids problems with large currents ?owing between

logic systems which are not initialized yet. Since both end voltages are differ-

ent, each converter reaches it’s setpoint voltage at a different time.

Figure 12 shows two POLs with different slew rates in order to reach differ-

ing ?nal voltages at about the same time.

Operation

To use the Sequence pin after power start-up stabilizes, apply a rising external

voltage to the Sequence input. As the voltage rises, the output voltage will

track the Sequence input (gain = 1). The output voltage will stop rising when it

reaches the normal set point for the converter. The Sequence input may option-

ally continue to rise without any effect on the output. Keep the Sequence input

voltage below the converter’s input supply voltage.

Use a similar strategy on power down. The output voltage will stay constant

until the Sequence input falls below the set point.

Any strategy may be used to deliver the power up/down ramps. The circuits

below show simple RC networks but you may also use operational ampli?ers,

D/A converters, etc.

Circuits

The circuits shown in Figures 5 through 13 introduce several concepts when

using these Sequencing controls on Point-of-Load (POL) converters. These

circuits are only for reference and are not intended as ?nal designs ready for

your application. Also, numerous connections are omitted for clarity.

Figure 10 shows a basic Master (POL A) and Slave (POL B) connected so that

the POL B ramps up identically to POL A as shown in timing diagram Figure?6.

RC?network R1 and C1 charge up at a rate set by the R1-C1 time constant,

giving a roughly linear ramp. As POL A reaches 3.3V out (the setpoint of POL?B),

POL B will stop rising. POL A then continues rising until it reaches 5V.

R1 should be selected so that it is signi?cantly smaller than the internal

bias current resistor from the Sequence pin. Start with a value of 20 Kilohms.

In Figure 10, we assume that the critical phase is only on power up therefore

there is no provision for ramped power down.

Figure 11 shows a single POL and the same RC network. However we have

added a small FET at Q1 to function as an up/down control. When V IN power is

?rst applied to the POL, Q1 is biased on, shorting out the Sequence pin. When

Q1’s gate is biased off, R1 now charges C1 and the POL’s output now ramps up

at the R1-C1 slew rate. Note that Q1’s gate would typically be controlled from

some external digital logic.

If you wish to have a ramped power down (rather than a step down), add a

small resistor in series with Q1’s drain.

Figure 12 shows both a RC ramp on Master POL A and a proportional track-

ing divider (R2 and R3) on POL B. We have also added an optional very small

noise ?lter cap at C2. Figure 12’s circuit corresponds roughly to Figure 7’s

timing for power up.

Guidelines for Sequence/Track Applications

[1] Leave the converter’s On/Off Enable control (if installed) in the On setting.

Normally, you should just leave the On/Off pin open.

[2] Allow the converter to stabilize (typically less than 20 mS after +V IN power

on) before raising the Sequence input. Also, if you wish to have a ramped

power down, leave +V IN powered all during the down ramp. Do not simply

shut off power.

[3] If you do not plan to use the Sequence/Track pin, leave it open.

[4] Observe the Output slew rate relative to the Sequence input. A rough

guide is 2 Volts per millisecond maximum slew rate. If you exceed this

slew rate on the Sequence pin, the converter will simply ramp up at

it’s maximum output slew rate (and will not necessarily track the faster

Sequence input). The reason to carefully consider the slew rate limitation

is in case you want two different POL’s to precisely track each other.

[5] Be aware of the input characteristics of the Sequence pin. The high input

impedance affects the time constant of any small external ramp capacitor.

And the bias current will slowly charge up any external caps over time

if they are not grounded. The internal pull up resistor to +V IN is typically

400?Kilohms to 1 Megohm.

Notice in the simpli?ed Sequence/Track equivalent circuit (Figure 13) that

a blocking diode effectively disconnects this circuit when the Sequence/

Track pin is left open.

[6] Allow the converter to eventually achieve its full rated setpoint output volt-

age. Do not remain in ramp up/down mode inde?nitely. The converter is

characterized and meets all its speci?cations only at the setpoint voltage

(plus or minus any trim voltage). During the ramp-up phase, the converter

is not considered fully in regulation. This may affect performance with

excessive high current loads at turn-on.

[7] The Sequence is a sensitive input into the feedback control loop of the

converter. Avoid noise and long leads on this input. Keep all wiring very

short. Use shielding if necessary.

[8] If one converter is slaving to another master converter, there will be a very

short phase lag between the two converters. This can usually be ignored.

[9] You may connect two or more Sequence inputs in parallel from two con-

verters. Be aware of the increasing pull-up bias current and reduced input

impedance.

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